# Xuanyao Fong Source: https://hello.cv/xuanyaofong ## Work ### Assistant Professor | National University of Singapore College of Design and Engineering ## Education ### Purdue University | Ph.D ### Purdue University | BSc ## Publications ### KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells 2011 International Conference on Simulation of Semiconductor Processes and Devices conference-paper ### KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells conference-paper ### Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches 2013 5th IEEE International Memory Workshop conference-paper ### Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches conference-paper ### R-MRAM: A ROM-Embedded STT MRAM Cache IEEE Electron Device Lett. journal-article ### Reading spin-torque memory with spin-torque sensors 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) conference-paper ### Reading spin-torque memory with spin-torque sensors conference-paper ### SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture IEEE Electron Device Lett. journal-article ### SPINTASTIC: Spin-based stochastic logic for energy-efficient computing conference-paper ### STT-MRAMs for future universal memories: Perspective and prospective 2012 28th International Conference on Microelectronics Proceedings conference-paper ### STT-MRAMs for future universal memories: Perspective and prospective conference-paper ### Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective IEEE Sensors J. journal-article ### Ultra-Low Power Nanomagnet-Based Computing: A System-Level Perspective IEEE Trans. Nanotechnology journal-article ### SHE-NVFF: Spin hall effect-based nonvolatile flip-flop for power gating architecture IEEE Electron Device Letters journal-article ### SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture IEEE Electron Device Letters journal-article ### R-MRAM: A ROM-embedded STT MRAM cache IEEE Electron Device Letters journal-article ### R-MRAM: A ROM-Embedded STT MRAM Cache IEEE Electron Device Letters journal-article ### Reading spin-torque memory with spin-torque sensors Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 conference-paper ### Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches 2013 5th IEEE International Memory Workshop, IMW 2013 conference-paper ### STT-MRAMs for future universal memories: Perspective and prospective 2012 28th International Conference on Microelectronics - Proceedings, MIEL 2012 conference-paper ### Spin-transfer torque MRAMs for low power memories: Perspective and prospective IEEE Sensors Journal journal-article ### Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective IEEE Sensors Journal journal-article ### Ultra-low power nanomagnet-based computing: A system-level perspective IEEE Transactions on Nanotechnology journal-article ### Ultra-Low Power Nanomagnet-Based Computing: A System-Level Perspective IEEE Transactions on Nanotechnology journal-article ### KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells International Conference on Simulation of Semiconductor Processes and Devices, SISPAD conference-paper ## Source Read this profile on Hello.cv: https://hello.cv/xuanyaofong Create your free profile at https://hello.cv